The present invention is directed to Direct Memory Access (DMA) controllers, and, more particularly, to a DMA controller with a trigger sequence generator.
Direct Memory Access is a technique for allowing data to be transferred to a memory, such as from a peripheral device, without intervention by a processor, which frees the processor to perform other tasks, in parallel. The data transfer task is managed by a DMA controller instead of the processor. FIG. 1 illustrates a conventional DMA controller 10 that is used on various integrated circuit chips, such as microcontroller units (MCU) and Digital Signal Processors (DSP). The DMA controller 10 is located between a first, high speed bus 12, such as AHB (Advanced High-performance Bus) or AXI (Advanced eXtensible Interface), and a lower speed slave bus 14. It is understood that the AHB and AXI bus masters are different in many aspects, but DMA controllers are available for both such systems. The speed bus 12 is used to move data to and from a memory (not shown). A processor such as a central processing unit (CPU) is connected to the DMA controller 10 via the low speed bus 14, and provides information to the DMA controller 10 to configure the DMA controller 10. That is, the CPU instructs the DMA controller 10 with how much data to move, where to get the data (source address) and where to move the data (destination address).
The DMA controller 10 includes a data path 16, an address path 18, control and arbitration logic 20, and DMA program model and data transfer descriptor logic 22. The data path 16 represents the path of the data to be transferred from a source address to a destination address, while the address path 18 is the path for the source and destination addresses. The control and arbitration logic 20 schedules the data exchange to the high-speed bus 12 and manages the data transfer by, for example, putting the source/destination addresses on the high-speed bus 12, and decrementing a counter (e.g., from 7 to 0 if moving 8 words) to control the loop. The DMA controller 10 executes operations by loading transfer configurations (e.g., descriptors) that describe all the details regarding the source/destination, burst size, length of the transfer, etc. The program model and data transfer descriptor logic 22 receives this descriptor information from the low-speed bus 14 to manage the transfer.
Upon the arrival of an external trigger, such as either a software trigger from the CPU or a hardware trigger initialized by an on-chip peripheral like a timer, and received by the DMA program model and data transfer descriptor logic 22, the DMA controller 10 will start to fetch data from a specified source address and move the fetched data to a specified destination address, until the specified amount of data has been transferred. As noted above, during this period, the processor (CPU) does not need to intervene during the data movement and therefore is liberated for other tasks or it may sleep.
In some cases, data movement is done periodically, with the interval between data transfers being either equidistant or non-equidistant. Initiating such periodic data movement can be done using a software trigger issued by the CPU or a hardware trigger from another on-chip peripheral, like a timer. If a software trigger from the CPU is used, the CPU must be kept awake so that it can trigger the DMA transfer requests. This is not efficient in some applications like metering or medical devices where power consumption is a critical design target. On the other hand, if an on-chip timer is used, software is needed to refresh the timing modulus of the timer for those cases where the interval between the DMA transfers is not evenly distributed, which also requires CPU intervention. Furthermore, for some chips there is only one timer resource available and it may be needed for other applications.
Accordingly, it would be advantageous to have a method of triggering DMA activities while allowing the CPU to sleep and at the same time not tying up other chip resources.